####################################################
# PARSE DESIGN CONFIGURATION
####################################################
set top_design top
set include_path {"." "src" "ip_core/dwip_v2_1/src"}
set verilog_design_files {"src/top.v" "src/soc_system_v1.v" "src/pll_v1.v" "src/debugware_v2_1.v" "src/apb2_fp_slave.v" "src/sram_v1.v" "src/oscillator_v1.v" "src/sram_test.v" "src/emb_v1.v" "ip_core/dwip_v2_1/src/dwip.v"}
set bbox_lib "$env(AGATE_ROOT)/data/lib/cst_lib_p0.v"
setmsgtype -ignore {VERI-1012}
setmsgtype -ignore {VERI-1141}
setmsgtype -error {VERI-1466}
setmsgtype -error {VERI-1084}
if {[info exists vhdl_design_files]} {
    source "$env(AGATE_ROOT)/data/syn/cfe/init_vhdl_lib.tcl"
    parse_design -work work -format vhdl -vhdl_2008 -vhdl_sort ${vhdl_design_files} -incdir ${include_path} -v ${bbox_lib} -print_message
}
if {[info exists verilog_design_files]} {
    parse_design -work work -format verilog ${verilog_design_files} -incdir ${include_path} -v ${bbox_lib} -print_message
}
dump_design_info -work work -format "verilog" -dump "C:/Users/Tanek/work/projects/hme/h7_project/board/HME-H7P20N0L176-M2H1_ETH_EVB/fpga/outputs/top_design_info.xml" -top "top"
exit 0